Low-Cost Test for Large Analog IC's

This paper outlines a basic block level test translation tool for analog systems. Test translation aims at minimizing DFT overhead in a hierarchical test translation scheme to meet the ever increasing integration, performance and test re-use requirements. The concept of analog signal propagation and necessary signal attributes are introduced to achieve e ective and accurate test translation. A pre-analysis of the system to identify feasible paths and utilization of behavioral basic block models provide computational e ectiveness. Experimental results show that test translation reduces DFT overhead signi cantly while satisfying coverage requirements.